This disclosure relates generally to a process and apparatus for fabricating an integrated circuit and, more particularly, to a process and apparatus for optically removing or reducing charge build-up that occurs during fabrication of integrated circuit devices.
A variety of integrated circuits employing non-volatile memory (NVM) arrays have been proposed or used in industry. Non-volatile memory arrays are generally based upon a floating gate technology. That is, a technology that generally refers to the transfer of a charge through an oxide or a dielectric layer into a conductive floating gate where it can be stored or removed. An example of a non-volatile memory array device employing floating gate technology is an erasable programmable read-only memory (xe2x80x9cEPROMxe2x80x9d) device that is readable, erasable and writeable, i.e., programmable. An EPROM generally employs a floating gate field effect transistor, which has binary states depending on the presence or absence of charge on the floating gate. Data is stored in the non-volatile memory device by the storage of electrical charge, e.g., electrons, in the floating gate.
Numerous varieties of EPROMs are available. In the traditional and most basic form, EPROMs are programmed electrically and erased by exposure to ultraviolet light. These types of EPROMs are commonly referred to as ultraviolet erasable programmable read-only memories (xe2x80x9cUVEPROM""sxe2x80x9d). UVEPROMs can be programmed by running a high current between a drain and a source of the UVEPROM transistor while applying a positive potential to the gate. The positive potential on the gate attracts energetic (i.e., hot) electrons from the drain-to-source channel current, where the electrons jump or inject into the floating gate and become trapped on the floating gate. UVEPROM""s based on this technology are designed to have their charge optically erased. In this manner, stored charge can be removed by exposing the device to ultraviolet light whenever re-programming is necessary.
An exemplary UVEPROM is shown in FIG. 1. The device, generally designated 10, includes a source region 12, and a drain region 14, formed on an n-type substrate 16. A gate oxide film 18 is formed on the substrate surface over a channel defined between the source region 12 and the drain region 14. A floating gate electrode 20 composed of p-type polysilicon or the like is typically disposed above the gate oxide film 18. Since UVEPROMs are designed to have their charge optically erased, any charge buildup that occurs during the fabrication process can be removed by exposing the device to ultraviolet light during the fabrication process.
Another form of EPROM is the electrically erasable programmable read-only memory also referred to as xe2x80x9cEEPROMxe2x80x9d or xe2x80x9cE2PROMxe2x80x9d. EEPROMs are often programmed and erased electrically by way of a phenomenon known as Fowler-Nordheim tunneling. These devices are not designed to be optically erased during operation. Consequently, dangerous charge buildup can occur during the fabrication of the integrated circuit.
Still another form of EPROM is a xe2x80x9cFlash EPROM,xe2x80x9d which is programmed using hot electrons and erased using the Fowler-Nordheim tunneling phenomenon. Flash EPROMs can be erased in a xe2x80x9cflashxe2x80x9d or bulk mode in which all cells in an array or a portion of an array can be erased simultaneously using Fowler-Nordheim tunneling. Flash EPROMs are commonly referred to as xe2x80x9cflash cellsxe2x80x9d or xe2x80x9cflash devices.xe2x80x9d Similar to EEPROM devices, charge buildup that occurs during fabrication of the flash EPROM device is not designed to be optically erased. As shown in FIG. 2, an exemplary EEPROM or flash EPROM device generally includes an additional conductive gate layer 22 disposed above the floating gate 20.
During fabrication of an integrated circuit, it is well known that undesirable charge buildup occurs such as on the floating gate of an EPROM device, if applicable, and/or other areas of the integrated circuit. This charge buildup can lead to high voltages and cause electrical damage to the circuitry if the charge buildup is not removed or neutralized. Charge buildup can readily occur during one or more of the numerous processing steps common to fabricating the integrated circuit. For example, charge buildup can occur during an annealing process, during metal ashing or etching processes, after via and pad formation steps, and the like. Integrated circuits typically employ 3 to 5 conductive metal layers, which during fabrication includes about 5 to about 7 processing steps that can contribute to charge buildup. It is important to erase the charge buildup as the device is being fabricated.
Current manufacturing processes strive to erase the charge buildup that occurs during the manufacture of integrated circuits, especially with integrated circuits employing non-volatile memory devices such as the above noted EEPROM and Flash memories. The use of electrical probes can be used to provide a temporary connection to the circuits in order to impose the required voltages to effect erasure of the charge buildup. However, this method is time consuming and not practical for high volume production. Erasure times using electrical probes are typically greater than about ten minutes per wafer and depending on the particular circuit design can be greater than one hour per wafer.
Charge buildup has also been removed by exposing the integrated circuit to narrow-band radiation sources. Current charge-removal processes utilize a mercury electrode lamp that produces a narrow-band spectrum at a wavelength of about 254 nanometers. The mercury lamp emits high-energy photons that propagate through the integrated circuit stack to impart energy to the stored electrons and other charges present. These energized electrons overcome the energy barriers that previously confined the electrons and other charges such that recombination can occur between the electrons and the electron holes or positive charges within the integrated circuit. The narrow-band UV light exposure also increases the mobility of charges on other areas of the integrated circuit.
In UVEPROMs, removal of charge buildup by exposure to narrow-band radiation sources is generally considered efficient since this type of device is originally configured for optical erasure during its operation. The oxide layers or dielectric layers disposed over the floating gate are transparent to the narrow-band radiation emitted by the mercury lamp at the wavelength of about 254 nm.
However, current processes employing narrow-band light sources are inefficient for removal of charge buildup in other types of integrated circuit devices such as those devices including a conductive (e.g., metal) gate layer disposed over the floating gate electrode (e.g., EEPROM, Flash memory and the like), or those including many layers of metal lines above the floating gate memory cell. As shown in FIG. 2, the presence of conductive gate layer 22 serves to block incident radiation from reaching the underlying floating gate electrode 20, greatly reducing its erase efficiency. As a result, current exposure tools require long exposure times (i.e., greater than about one or two hours per wafer depending on the particular IC design) to reduce the charge buildup.
Exposure times are directly dependent on the intensity of the light source (as well as other factors). Source intensities of the current-art light sources employed in exposure tools are limited to, for example, about 30 milliwatts per square centimeter (mW/cm2) on average, and up to about 60 mW/cm2 when the lamps are new. Moreover, the narrow-band light sources utilized produce an emission signal comprising discrete and narrow spectral lines with low total output intensity at each line. Although the spectral output of prior art light sources can be varied to some extent, the resulting spectral lines do not contain much power or light intensity output apart from the primary emission at about 254 nm.
Current light sources employed for reducing charge buildup rely on bulb technology that includes the use of internal electrodes. The intensity of bulbs utilizing internal electrodes is known to deteriorate significantly over the usable life of the bulb. Users often allow the intensities to drop to as low as 50% of the intensity (compared to new) before replacing the bulbs in order to minimize the replacement expense. As a result, a decrease in throughput occurs as the bulb progressively deteriorates over time. Other problems resulting from the use of prior art bulbs include long cool down times for the lamps (up to several hours) such that replacement of the bulb often requires significant downtime to allow the bulb to cool. In addition, these types of bulbs exhibit a high failure rate upon re-ignition after the lamp is turned off. As a result, many integrated circuit manufacturers typically do not turn the bulbs off during periods of non-use, which drastically affects the useable operating lifetimes for the bulbs as well as increasing operating costs.
In addition to the inefficiencies of utilizing prior art light sources, current exposure tools have a relatively large footprint that requires a significant amount of floor space. Moreover, the exposure tools typically require manual loading of the wafers into the tool. This process is oftentimes today the only remaining step in a fab that requires manual handling. Manual handling is a serious disadvantage since it allows the possibility of wafer breakage or wafer damage (e.g., scratches), it requires additional labor investment, it allows for possible wafer contamination, and it does not easily provide for automatic wafer tracking.
There is clearly a need for an improved process for reducing charge buildup during the manufacture of integrated circuits, and especially with those integrated circuits utilizing non-volatile memory devices. Advanced design rules are further shrinking the patterns used for fabricating the integrated circuit. Concurrently, more metal line layers are being added, with the metal lines closer together since the minimum line and space dimensions also shrink. The net result is that it becomes more difficult for light of a given narrow-band wavelength to penetrate the IC structure and erase the charge buildup that occurs during the fabrication process.
Disclosed herein are processes and an apparatus for removing charge buildup that occurs during the manufacture of integrated circuits. In one embodiment, a process for removing charge buildup during fabrication of an integrated circuit comprises exposing the integrated circuit to a broadband radiation pattern at an intensity and exposure time effective to reduce the charge build-up occurring during fabrication of the integrated circuit.
In another embodiment, a process for reducing a charge buildup on a floating gate electrode during fabrication of an integrated circuit comprises placing the integrated circuit into a process chamber, wherein the integrated circuit comprises the floating gate electrode; and exposing the integrated circuit to a broadband radiation pattern at an intensity and exposure time effective to reduce the charge buildup.
Preferably, the broadband radiation pattern comprises at least one wavelength less than about 280 nanometers with a FWHM greater than about 10 nanometers.